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| CALIFORNIA MICRO DEVICES PAC VGA-100/101 VGA PROTECTION AND TERMINATION NETWORK Features 7 channel ESD protection 15KV ESD protection (HBM) 8KV contact, 15KV air discharge ESD protection per IEC 1000-4-2 (Level 4) Low loading capacitance, 4.5pF typical Application ESD protection for VGA (video) port in PCs and notebooks. Product Description The PAC VGA-100/101 acts as a transmission line terminating and ESD protection device. It provides 75 Ohm parallel terminations for the R, G, B lines and series terminations for the Horizontal and Vertical Sync lines and two monitor ID lines which provide Plug and Play logic signals. In addition, all interface lines provide Level 4 ESD protection per the IEC1000-4-2 contact discharge Specification. The PAC VGA-100 provides internal pull-up resistors for the two monitor ID lines. The PAC VGA-101 omits these internal pull-ups so that different pull-up resistor values can be added externally. ABSOLUTE MAXIMUM RATINGS SCHEMATIC CONFIGURATION Diode Forward DC Current (Note 1) 20mA Storage Temperature -65C to 150C Operating Temperature Range 0C to 70C DC Voltage at any Channel Input VN-0.5V to VP+0.5V Note 1: Only one diode conducting at a time. Typical Connection Diagram R1=75, R2=33, R3=2.2K (VGA-100 only) (*) R3 Removed (VGA-101 only) (**) For best ESD protection, minimize trace lengths between PAC VGA-100/101 and the video connector. (c)1999 California Micro Devices Corp. All rights reserved. (c)1999 California Micro Devices Corp. AllPAC is a trademark of California Micro Devices. P/Active(R) is a registered trademark and rights reserved. 1 / 99 215 Topaz Street, Milpitas, California 95035 1/ 99 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Tel: (408) 263-3214 C0170997D 1 Fax:Fax: (408) 263-7846 www.calmicro.com (408) 263-7846 www.calmicro.com 1 CALIFORNIA MICRO DEVICES PAC VGA-100/101 STANDARD SPECIFICATIONS Param e te r Min. Operating Supply Voltage ( V P - V N ) R/G/B termination resistor (R1) tolerance Series termination resistor (R2) tolerance Monitor ID pull-up resistor resistor (R3) tolerance 0.65V Diode Forward Voltage, I F = 20mA, T = 25C Diode reverse breakdown voltage, T = 25C 17.0V 000Top Diode (Cathode to V P ) 000Bottom Diode (Anode to V N ) 25.0V ESD Protection Peak Discharge Voltage at pins 7, 9, 11 and 14 -4KV 000Human Body Model, Method 3015 (Note 6) Peak Discharge Voltage at pins 2, 3, 5, 6, 10, 12, 15 000In-system (Note 2) -15KV 000Human Body Model, Method 3015 (Notes 3, 4) -8KV 000Contact Discharge per IEC 1000-4-2 (Note 5) Channel Clamp Voltage @ 15KV ESD HBM, T = 25C at pins 2, 3, 5, 6, 10, 12, 15. (Notes 3, 4) 000Positive transients 000Negative transients Channel Leakage Current, T = 25C Channel Input Capacitance (Measured @ 1 MHz) VP = 5V, VN = 0V, V I N P U T = 2 .5 V Package Power Rating 000QSOP Package Note Note Note Note Note 2: 3: 4: 5: 6: Typ. M a x. 5.5V 5% 5% 10% 0.95V +4KV +15KV +8KV V P + 13.0V V N - 13.0V 1.0 A 0.1 A at pins 2, 3, 5, 6, 10, 12, 15. 4.5pF 7pF 800mW From I/O pins to VP or VN only. VP bypassed to VN with 0.2 F ceramic capacitor. Human Body Model per MIL-STD-883, Method 3015, CDischarge=100pF, RDischarge=1.5K, VP=5V, VN=GND. This parameter is guaranteed by characterization. Standard IEC1000-4-2 with CDischarge=150pF, and RDischarge=330, VP=5V, VN=GND. These pins are not connected directly to the video connector, and therefore are not subject to direct ESD strikes. Application Information: See California Micro Devices Application Note AP-209 Design Considerations for ESD Protection Pins 16 16 Pa c k a g e STANDARD PART ORDERING INFORMATION Orde ring Part N um be r Style Tube s Tape & R e e l QSOP QSOP PACVGA-100/T PACVGA-101/T PACVGA-100/R PACVGA-101/R Part Mark ing PACVGA100 PACVGA101 (c)1999 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 / 99 |
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